Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric layers such as silicon dioxide and conductive paths or interconnects made of conductive materials. Interconnects are usually formed by filling a conductive material such as copper in trenches etched into the dielectric layers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in different layers can be electrically connected using vias or contacts.
The filling of copper into features such as vias, trenches, pads or contacts, can be carried out by electrodeposition. In electrodeposition or electroplating method, copper is deposited over the substrate surface including such features. As exemplified in FIG. 1, a substrate 10, for example a silicon wafer may have features, such as a via 12 and trenches 14 or other features of interest, etched into an insulating layer 16 on the substrate. Such features may form the wiring lines of an integrated circuit. The features and the top surface 18 (field region) of the insulating layer 16 are then coated with a suitable barrier layer and a seed layer. Exemplary barrier layer materials may be TaN, TaN/Ta and TiN, etc., and their various combinations. After the barrier layer deposition, a seed layer is typically coated on the barrier layer. For copper interconnect applications, a thin seed layer of copper or copper alloy is deposited over the barrier layer. Thickness of the seed layer is typically 50 to 100 nm. After the seed layer deposition step, the features are filled with a copper layer using an electroplating process. The plating process, in addition to filling the features with copper, also deposits excess copper over the top surface of the substrate. This excess copper is called an “overburden” and is removed after heat-treating it. After an annealing step, a material removal technique such as chemical mechanical polishing, electrochemical mechanical polishing, electropolishing, and chemical etching may be employed to planarize and remove the excess copper and barrier from the top surface, leaving conductors only in the features or cavities. In standard plating processes, this overburden copper is thicker than the depth of the features and has a large topography since large features on the wafer are coated in a conformal manner. For example, a wafer with 0.5 micron deep features may be coated with 0.8 micron thick copper by the standard ECD process, to assure complete, defect-free filling of all the features, including those that are wider than about 5 microns. The resulting copper surface then may have a topography that has a step of about 0.5 microns over the large features.
Conventionally, after the annealing, CMP process is employed to first globally planarize this topographic surface and then to reduce the thickness of the overburden copper layer down to the level of the surface of the barrier layer, which is also later removed leaving conductors only in the cavities. However, CMP is a costly and time consuming process and high pressures used in the CMP processes also damage low-k dielectrics, which are mechanically weaker than the silicon oxide. Therefore, minimizing CMP step in an integration process is a goal for all IC manufacturers. The topography on the wafers also causes problems for the CMP process. Specifically, the large steps such as the 0.5 micron step of the above example over the large features such as 100 micron wide trenches or bond-pads, cause dishing defects after CMP. Therefore, both in terms of cost and enabling features, it is very attractive to have thinner copper deposits with reduced surface topography on wafers.
Regardless of their thickness, however, plated films need to be annealed subsequent to copper plating process to stabilize their micro-structure by grain growth and re-crystallization. Larger grain size reduces the electrical resistivity of the copper film and improves its electromigration properties. Structures with larger grain size have lower electrical resistivity and lower density of grain boundaries, thus they are desirable. Conventionally, a copper plated substrate is generally annealed at temperatures, typically between 90° C. to 450° C., for a period of time, which may vary from a few seconds to 4 hours. In general, during the anneal, thickness of the copper overburden affects the grain growth and re-crystallization of the copper film within the features. If the copper overburden is thick, annealing process produces large grain size. Similarly, thin copper layer produces small grain size copper. However, as described above, thick overburden increases the cost of CMP process, and therefore; it is not economic.
As the thickness of the copper deposits is reduced, the impact of the nature of the barrier and seed layers and the seed layer thickness on the grain size of the interconnect becomes dominant. FIG. 2 is a schematic view of the via 12 having a thin copper overburden. As shown in FIG. 2, a barrier layer 20 is formed, using conventional deposition methods, to cover the walls and the bottom of the via 12 and the field region 18. Typical barrier layer thickness is in the range of 10–30 nm. After forming the barrier layer 20, a copper seed layer 22 is coated on the barrier layer. Conventional seed layer deposition methods results in thicker seed layers (TSeed1) over the field regions for example seed layers having 100 nm thickness. After the seed layer deposition a copper layer 24 is electroplated into the via and over the field region. Thickness of the copper layer (TCu) deposited on the seed layer at the field region is kept for example in the range of the 100 nm.
As mentioned before, with such thin copper layers, the effect of the seed layer on the grain size of the electroplated interconnect during the anneal becomes dominant. Seed layers inherently have small grain size and therefore have higher electrical resistivity. Especially in the vias and narrow trenches, thicker seed layers increase the volume of small grain size copper in the overall volume of the interconnect. As shown in FIG. 2, barrier and seed layers also occupy a significant volume of the thin overburden layer. Although the annealing process may induce grain growth in the seed layer along with the grain growth in the electroplated copper, the rate of grain growth in the seed layer is significantly lower. In FIG. 2, since about 50% of the overburden film is seed layer, grain growth in the overburden film will be limited. This limited grain growth would also affect grain growth within the feature in a negative way.
A much higher annealing temperature will be needed to fully transform the copper in the seed layer and the plated layer. As mentioned above, while higher temperature may be required to anneal such structures having thin overburden layers, high temperature anneals often result in higher stress. As the aspect ratio of the vias increases, via pullout type of defects become more wide spread. Such via separation from the underlying structure results in very high contact resistance and poor interconnect yield.